Low Density Parity Code (LDPC) decoders are current generation iterative soft-input forward error correction (FEC) decoders that have found increasing popularity in FEC applications where low error floor and high performance are desired. LDPC decoders are defined in terms of a two-dimensional matrix, referred to as an H matrix, which describes the connections between the data and the parity. The H matrix comprises rows and columns of data and parity information. Decoding an LDPC code requires solving the LDPC code according to the H matrix based on a two-step iterative method. Soft-decision decoding the code causes convergence of the solved code with the true code; convergence is achieved over a number of iterations and results in a corrected code with no errors.
A category of LDPC codes, known as quasi-cyclic (QC) codes, generates an H matrix with features that improve the ease of implementing the LDPC encoder and decoder. In particular, it is possible to generate a QC-LDPC H matrix where some rows are orthogonal to each other. These orthogonal rows are treated as a layer, and rows within a layer can be processed in parallel, thus reducing the iterative cost of the decoder. It is advantageous to reduce the number of iterations necessary to decode an LDPC code.
The standard criteria for determining when to exit the soft-decision decoding iterations uses check node outputs to determine when the decoder has converged. This is an area efficient exit criteria, but requires nearly a full iteration of extra run time beyond the iteration in which the decoder has converged. This full iteration cost is especially steep at typical operating points for an LDPC code where it is desirable to have codes that are converging in as few iterations as possible. For instance, if an operating point is defined by code convergence in an average of 5 iterations, then an extra iteration to determine exit status costs on the order of 20% more time and power. Even when the average convergence is 10 iterations, the exit status determination will cost approximately 10% more time and power than necessary.
One known approach to allow the decoder to exit as soon as possible comprises adding a check processor to recheck all parity equations after every soft-decision decoding iteration. Full parity check exit determination is most suitable for small fixed code LDPC decoders. However, while such an approach overcomes the extra iteration of the standard method, the additional check processor comes at the cost of a large area footprint, even for a small fixed code LDPC code. Large FEC block LDPC codes are advantageous for various reasons relating to reduced overhead; however, full parity check exit determination of a large FEC block LDPC code is difficult to implement due to the necessity of routing massive XOR trees.
Known LDPC decoders are also adversely affected by codeword loading and unloading to and from the codeword memory of the LDPC decoder. When loading a codeword from a decoder input into the memory of the decoder, or when unloading a codeword from the memory to the output of the decoder, the decoder core is unable to access the memory and remains idle, reducing the overall decoding speed of the LDPC decoder.
Improvements to error decoding methods and decoders are desirable.